The present disclosure relates to a device for determining an estimate of the logarithm of an input variable, to a corresponding method and to a corresponding computer program product.
The calculation of the logarithmic function has been available since approximately 1990 in many floating point processors as an installed hardware function, and is usually accomplished by an integrated floating point coprocessor. Alternatively, the logarithmic calculation is performed by software (so-called floating point emulation), and this naturally takes place much more slowly. It is usual here to use iterative methods which require a plurality of steps to calculate the logarithm.
Likewise to be found in fixed point arithmetic are methods which calculate the logarithm in a plurality of steps, or else calculate the logarithm in one step. Methods which calculate the logarithm in one step mostly have a stipulated accuracy of the calculation and cannot be adapted to any desired accuracy.
The scientific publication by Mitchell, J. N., “Computer Multiplication and Division Using Binary Logarithms”, IRE Transactions on Electronic Computers, 1962, EC-11, 517 describes in this context an algorithm for electronic calculation of logarithms in electronic processors.